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ADM1276
Data Sheet
FAST RESPONSE TO SEVERE OVERCURRENT
SYSTEM CONTROL
V IN
ADM1276
The ADM1276 features a separate high bandwidth current
sense amplifier that is used to detect a severe overcurrent that
is indicative of a short-circuit condition. A fast response time
EN
D1
R1
UV
V IN
R SENSE
allows the ADM1276 to handle events of this type that could
otherwise cause catastrophic damage if not detected and acted
on very quickly. The fast response circuit ensures that the
ADM1276 can detect an overcurrent event at approximately
200% to 250% of the normal current limit (ISET) and can
respond to and control the current within 1 μs, in most cases.
UNDERVOLTAGE AND OVERVOLTAGE
The ADM1276 monitors the supply voltage for undervoltage
(UV) and overvoltage (OV) conditions. The UV and OV pins
are connected to the input of an internal voltage comparator,
and its voltage level is internally compared with a 1 V voltage
reference.
An external resistor network divides the supply voltage for moni-
toring. An undervoltage event is detected when the voltage
connected to the UV pin falls below 1 V, and the gate is shut
down using the 10 mA pull-down device. Similarly, when an
overvoltage event occurs and the voltage on the OV pin exceeds
1 V, the gate is shut down using the 10 mA pull-down device.
Q1
R2
Figure 50. Using the UV Pin as an Enable
Diode D1 prevents the external driver pull-up from affecting
the UV threshold. Select Diode D1 using the following criteria:
( V F × D1 ) + ( V OL × EN ) << 1.0 V ( I F = V IN / R1 )
Ensure that the EN sink current does not exceed the specified V OL
value. If the open-drain device has no pull-up, the diode is not
required.
POWER GOOD
The power good (PWRGD) output can be used to indicate
whether the output voltage is above a user-defined threshold
and can, therefore, be considered good. The PWRGD output is
derived using the FLB resistor network, composed of R1 and R2
The PWRGD pin is an open-drain output that pulls low when
the voltage at the FLB pin is lower than 1.1 × V ISET (power bad).
When the voltage at the FLB pin is above this threshold (indicating
SENSE+
SENSE–
that the output voltage has risen), the open-drain pull-down is
VCC
+
×50
–
ADM1276
disabled, allowing PWRGD to be pulled high. PWRGD is
guaranteed to be in a valid state for VCC ≥ 1 V.
UV
OV
+
1V –
–
1V +
IOUT
GATE
DRIVE
GATE
Hysteresis on the FLB pin is provided by a 2 μA internal current
source that is switched on when the V FLB input voltage exceeds the
input threshold. The current source is disconnected when V OUT
drops below the foldback threshold voltage minus the hysteresis
GND
Figure 49. Undervoltage and Overvoltage Supply Monitoring
ENABLE INPUT
The ADM1276 provides a dedicated ENABLE digital input pin.
voltage. Resistor R3 is internal to the ADM1276 . The hysteresis
voltage at the FLB pin can be varied by adjusting the parallel
combination of Resistor R1 and Resistor R2.
2μA
The ENABLE pin allows the ADM1276 to remain off by using a
hardware signal, even when the voltage on the UV pin is above
1.0 V and the voltage on the OV pin is less than 1.0 V. Although
V OUT
R1
FLB
R3
SWITCH IS ON WHEN
COMPARATOR OUTPUT IS HIGH
the UV pin can be used to provide a digital enable signal, using
the ENABLE pin for this purpose means that the ability to
monitor for undervoltage conditions is not lost.
In addition to the conditions for the UV and OV pins, the
ADM1276 ENABLE input pin must be high for the device
to begin a power-up sequence.
R2
1.3kΩ
1.1 × V ISET
Figure 51. Generation of PWRGD Signal
PWRGD
A similar function can be achieved using the UV pin directly.
Alternatively, if the UV divider function is still required, the
configuration shown in Figure 50 can be used.
Rev. C | Page 22 of 48
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